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Tj is calculated by either of the following equations.

● Tj = Ta + θja × Total power consumption

● Tj = Tt + Ψjt × Total power consumption

Tj : Junction temperature (°C)

Ta : Ambient temperature (°C)

Tt : Top center case temperature (°C)

θja : Thermal resistance of “Junction”-to-“Ambient” (°C/W)

Ψjt : Thermal resistance of “Junction”-to-“Top center case” (°C/W)

● Total power consumption = Voltage × (Leakage current + Dynamic current)

● Leakage current of IO = Σ (IOL × VOL) / Voltage + Σ (|IOH| × |VCC – VOH|) / Voltage

● Dynamic current of IO = Σ IO (Cin + Cload) × IO switching frequency × Voltage

Cin: Input capacitance

Cload: Output capacitance

Regarding θja and Ψjt, see Table 2.16.

Table 2.16

Thermal resistance

Parameter

Package

Symbol

Value*1

Unit

Test conditions

Thermal resistance

48-pin HWQFN

θja

18.0

℃/W

JESD 51-2 and 51-7

compliant

48-pin LQFP

59.7

64-pin LQFP

50.8

80-pin LQFP

52.0

100-pin LQFP

52.2

48-pin HWQFN

Ψjt

0.14

℃/W

JESD 51-2 and 51-7

compliant

48-pin LQFP

1.97

64-pin LQFP

1.48

80-pin LQFP

1.48

100-pin LQFP

1.48

Note 1. The values are reference values when the 4-layer board is used. Thermal resistance depends on the number of layers or size of the

board. For details, see the JEDEC standards.

2.3

AC Characteristics

2.3.1

Frequency

Table 2.17

Operation frequency in high-speed operating mode

Conditions: VCC = AVCC0 = 1.8 to 5.5 V

Parameter

Symbol

Min

Typ

Max*4

Unit

Operation

frequency

System clock (ICLK)*1*2

1.8 to 5.5 V

0.032768 —

MHz

Peripheral module clock (PCLKB)

1.8 to 5.5 V

—

Peripheral module clock (PCLKD)*3

1.8 to 5.5 V

—

Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for programming or

erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as

1.5 MHz cannot be set.

Note 2. The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy

of the clock source.

Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC12 is in use.

Note 4. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed

operation, see Table 2.21.

RA2L1 Datasheet

2. Electrical Characteristics

R01DS0385EJ0160 Rev.1.60

Oct 14, 2025

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