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R7KA8M2AFDCAC Scheda tecnica(PDF) 62 Page - Renesas Technology Corp |
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R7KA8M2AFDCAC Scheda tecnica(HTML) 62 Page - Renesas Technology Corp |
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62 / 295 page ![]() Table 2.13 Current of high-speed mode, maximum data processing (MVE operation), peripheral clock ON (External VDD mode) Parameter Symbol Typ Max Unit Test conditions 95 °C 105 °C 125 °C Supply current *1*2 CPUCLK0 = 1 GHz CPUCLK1 = 250 MHz VCL = voltage range 1 IDD*3 350 827 — — mA *4 CPUCLK0 = 800 MHz CPUCLK1 = 200 MHz VCL = voltage range 1 IDD*3 290 — 874 — CPUCLK0 = 600 MHz CPUCLK1 = 200 MHz VCL = voltage range 1 IDD*3 241 — — 915 CPUCLK0 = 600 MHz CPUCLK1 = 150 MHz VCL = voltage range 2 IDD*3 226 692 798 879 Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state. Note 2. Measured with clocks supplied to the peripheral functions and peripherals being operated. This does not include the BGO operation. Note 3. IDD depends on f (CPUCLK0 and ICLK) as follows. The ICLK items in the formula include CPU1 current. IDD Typ. = 0.24 × fCPUCLK0 + 0.37 × fICLK + 21 (unit : mA, fCPUCLK0 and fICLK are MHz) IDD Max.(VCL = voltage range 1, 95℃) = 0.27 × fCPUCLK0 + 0.20 × fICLK + 477 (unit : mA, fCPUCLK0 and fICLK are MHz) IDD Max.(VCL = voltage range 1, 105℃) = 0.27 × fCPUCLK0 + 0.20 × fICLK + 553 (unit : mA, fCPUCLK0 and fICLK are MHz) IDD Max.(VCL = voltage range 1, 125℃) = 0.27 × fCPUCLK0 + 0.20 × fICLK + 709 (unit : mA, fCPUCLK0 and fICLK are MHz) IDD Max.(VCL = voltage range 2, 95℃) = 0.27 × fCPUCLK0 + 0.18 × fICLK + 464 (unit : mA, fCPUCLK0 and fICLK are MHz) IDD Max.(VCL = voltage range 2, 105℃) = 0.27 × fCPUCLK0 + 0.18 × fICLK + 537 (unit : mA, fCPUCLK0 and fICLK are MHz) IDD Max.(VSCR_2, 125℃) = 0.27 × fCPUCLK0 + 0.18 × fICLK + 691 (unit : mA, fCPUCLK0 and fICLK are MHz) Note 4. Same frequency condition is applied as in the maximum condition. RA8M2 Datasheet 2. Electrical Characteristics R01DS0438EJ0130 Rev.1.30 Feb 27, 2026 Page 62 of 295 |
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