R7KA8M2AFDCAC datasheet(2/295 Pages) RENESAS

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Overview

The MCU integrates multiple series of software-compatible Arm®-based 32-bit cores that share a common set of Renesas

peripherals to facilitate design scalability and efficient platform-based product development.

The MCU in this series incorporates a high-performance Arm® Cortex®-M85 core running up to 1 GHz and Arm®

Cortex®-M33 core running up to 250 MHz with the following features:

● Up to 1 MB MRAM

● 2 MB SRAM (256 KB of CM85 TCM RAM, 128 KB CM33 TCM RAM, 1664 KB of user SRAM)

● Octal Serial Peripheral Interface (OSPI)

● Layer 3 Ethernet Switch Module (ESWM), USBFS, USBHS, SD/MMC Host Interface

● Analog peripherals

● Security and safety features

1.1

Function Outline

Table 1.1

Arm core

Feature

Functional description

Arm® Cortex®-M85 core

● Maximum operating frequency: up to 1 GHz

● Arm® Cortex®-M85 core

– Revision: (r1p1-00rel0)

– ARMv8.1-M architecture profile

– Armv8-M Security Extension

– Floating Point Unit (FPU) compliant with the ANSI/IEEE Std 754-2008

Scalar half, single, and double-precision floating-point operation

– M-profile Vector Extension (MVE)

Integer, half-precision, and single-precision floating-point MVE (MVE-F)

● Arm® Memory Protection Unit (Arm MPU)

– Protected Memory System Architecture (PMSAv8)

– Secure MPU (MPU_S): 8 regions

– Non-secure MPU (MPU_NS): 8 regions

● SysTick timer

– Embeds two Systick timers: Secure instance (SysTick_S) and Non-secure instance

(SysTick_NS)

– Driven by CPUCLK0 or MOCO divided by 8

● CoreSight™ ETM-M85

Arm® Cortex®-M33 core

● Maximum operating frequency: up to 250 MHz

● Arm® Cortex®-M33 core

– Revision: (r0p4-00rel2)

– ARMv8-M architecture profile

– Armv8-M Security Extension

– Armv8-DSP Extension

– Floating Point Unit (FPU) compliant with the ANSI/IEEE Std 754-2008 single-precision

floating-point operation

● Arm® Memory Protection Unit (Arm MPU)

– Protected Memory System Architecture (PMSAv8)

– Secure MPU (MPU_S): 8 regions

– Non-secure MPU (MPU_NS): 8 regions

● SysTick timer

– Embeds two Systick timers: Secure instance (SysTick_S) and Non-secure instance

(SysTick_NS)

– Driven by CPUCLK1 or MOCO divided by 8

● CoreSight™ ETM-M33

Table 1.2

Memory (1 of 2)

Feature

Functional description

Code MRAM

Maximum 1 MB of code MRAM.

Flash memory

System in package (SiP) maximum 8 MB serial flash memory.

Option-setting memory

The option-setting memory determines the state of the MCU after a reset.

RA8M2 Datasheet

1. Overview

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 2 of 295

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