R5F564MLGDFP datasheet(80/162 Pages) RENESAS

80 / 162 page

R01DS0173EJ0120 Rev.1.20

Page 80 of 162

Oct 20, 2022

RX64M Group

2. Electrical Characteristics

Figure 2.10

PLL Clock Oscillation Start Timing

Note 1. When using a sub-clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation

provided by the manufacturer for the oscillation stabilization time.

Note 2. The number of cycles selected by the value of the SOSCWTCR.SSTS[7:0] bits determines the sub-clock oscillation stabilization

wait time in accord with the formula below.

tSUBOSCWT = [(SSTS[7:0] bits × 16384) + 10] / fLOCO

Figure 2.11

Sub-Clock Oscillation Start Timing

Table 2.18

PLL Clock Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Test

Conditions

PLL clock oscillation frequency

fPLL

120

—

240

MHz

PLL clock oscillation stabilization wait time

tPLLWT

—

259

320

µs

Figure 2.10

Table 2.19

Sub-Clock Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7

≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

VBATT = 2.0 to 3.6 V, Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Test

Conditions

Sub-clock oscillation frequency

fSUB

—

32.768

—

kHz

Sub-clock oscillation stabilization time

tSUBOSC

——

Figure 2.11

Sub-clock oscillation stabilization wait time

tSUBOSCWT

——

PLLCR2.PLLEN

OSCOVFSR.PLOVF

PLL clock

tPLLWT

PLL circuit output

Sub-clock oscillator output

SOSCCR.SOSTP

tSUBOSC

Sub-clock

OSCOVFSR.SOOVF

tSUBOSCWT

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