Data Sheet

AD5273

Rev. J | Page 5 of 20

Parameter

Symbol

Test Conditions/Comments

Min

Typ1

Max

Unit

DYNAMIC CHARACTERISTICS7, 13, 14

Bandwidth, −3 dB

BW_1 kΩ

R

AB = 1 kΩ, code = 0x20

6000

kHz

BW_10 kΩ

R

AB = 10 kΩ, code = 0x20

600

kHz

BW_50 kΩ

R

AB = 50 kΩ, code = 0x20

110

kHz

BW_100 kΩ

R

AB = 100 kΩ, code = 0x20

60

kHz

Total Harmonic Distortion

THD

W

V

A = 1 V rms, RAB = 1 kΩ, VB = 0 V,

f = 1 kHz

0.05

%

Adjustment Settling Time

t

S1

V

A = 5 V ± 1 LSB error band,

V

B = 0 V, measured at VW

5

µs

Power-Up Settling Time—

After Fuses Blown

t

S2

V

A = 5 V ± 1 LSB error band,

V

B = 0 V, measured at VW, VDD = 5 V

5

µs

Resistor Noise Voltage

e

N_WB

R

AB = 1 kΩ, f = 1 kHz, code = 0x20

3

nV/√Hz

INTERFACE TIMING CHARACTERISTICS7,14,15

Applies to all parts

SCL Clock Frequency

f

SCL

400

kHz

t

BUF Bus Free Time Between

Stop and Start

t

1

1.3

µs

t

HD; STA Hold Time

(Repeated Start)

t

2

After this period, the first clock

pulse is generated

0.6

µs

t

LOW Low Period of SCL Clock

t

3

1.3

µs

t

HIGH High Period of SCL Clock

t

4

0.6

50

µs

t

SU; STA Setup Time for

Start Condition

t

5

0.6

µs

t

HD; DAT Data Hold Time

t

6

0.9

µs

t

SU; DAT Data Setup Time

t

7

0.1

µs

t

F Fall Time of Both SDA and

SCL Signals

t

8

0.3

µs

t

R Rise Time of Both SDA and

SCL Signals

t

9

0.3

µs

t

SU; STO Setup Time for Stop Condition

t

10

0.6

µs

OTP Program Time

t

11

400

ms

1 Typical values represent average readings at 25°C, V

DD = 5 V, and VSS = 0 V.

2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3 V

AB = VDD, wiper (VW) = no connect.

4 ∆R

WB/∆T = ∆RWA/∆T. Temperature coefficient is code-dependent; see the Typical Performance Characteristics section.

5 INL and DNL are measured at V

W. INL with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VW with the RDAC configured as a

potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating

conditions.

6 The A, B, and W resistor terminals have no limitations on polarity with respect to each other.

7 Guaranteed by design; not subject to production test.

8 The minimum voltage requirement on the V

IH is 0.7 × VDD. For example, VIH min = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD.

However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.

9 Different from the operating power supply; the power supply for OTP is used one time only.

10 Different from the operating current; the supply current for OTP lasts approximately 400 ms for the one time it is needed.

11 See Figure 28 for the energy plot during the OTP program.

12 P

DISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

13 Bandwidth, noise, and settling time depend on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.

The highest R value results in the minimum overall power consumption.

14 All dynamic characteristics use V

DD = 5 V.

15 See Figure 29 for the location of the measured values.