AD5273BRJZ10-R2 datasheet(15/20 Pages) AD

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Data Sheet

AD5273

Rev. J | Page 15 of 20

ent temperature coefficients, the ratiometric adjustment also

reduces the overall temperature coefficient effect to 5 ppm/°C,

except at low value codes where RW dominates.

Potentiometer mode includes op amp feedback resistor networks

and other voltage scaling applications. Terminal A, Terminal W,

and Terminal B can in fact be input or output terminals, provided

that |VAB|, |VWA|, and |VWB| do not exceed VDD to GND.

ESD PROTECTION

Digital inputs SDA and SCL are protected with a series input

resistor and parallel Zener ESD structures (see Figure 36).

Figure 36. ESD Protection of Digital Pins

TERMINAL VOLTAGE OPERATING RANGE

There are also ESD protection diodes between VDD and the

RDAC terminals. The VDD of AD5273 therefore defines their

voltage boundary conditions (see Figure 37). Supply signals

present on Terminal A, Terminal B, and Terminal W that exceed

VDD are clamped by the internal forward-biased diodes.

Figure 37. Maximum Terminal Voltages Set by VDD

POWER-UP/POWER-DOWN SEQUENCES

Because of the ESD protection diodes, it is important to power

VDD first before applying any voltages to Terminal A, Terminal B,

and Terminal W. Otherwise, the diode is forward-biased such that

VDD is powered unintentionally and can affect the rest of the user’s

circuits. The ideal power-up sequence is in the following order:

GND, VDD, digital inputs, and VA/VB/VW. The order of powering

VA, VB, VW, and digital inputs is not important as long as they are

powered after VDD. Similarly, VDD should be powered down last.

POWER SUPPLY CONSIDERATIONS

To minimize the package pin count, both OTP and normal opera-

ting voltage supplies are applied to the same VDD terminal of the

AD5273. The AD5273 employs fuse link technology that requires

from 5 V to 5.5 V for all end to end resistance options, for

blowing the internal fuses to achieve a given setting, but normal

VDD can be in the range of 2.7 V to 5.5 V after completing the

fuse programming process. As a result, dual voltage supplies and

isolation are needed if the system VDD is outside the required

VDD_OTPrange. For successful OTP, the fuse programming supply

(either an on-board regulator or rack-mount power supply)

must be rated at 5 V to 5.5 V for all end to end resistance

options, and be capable of sourcing 100 mA for 400 ms. When

fuse programming is completed, the VDD_OTP supply can be

removed to allow normal operation of 2.7 V to 5.5 V; the device

then reduces the current consumption to the µA range.

When operating systems at 2.7 V, use of the bidirectional low

threshold P-Ch MOSFETs is recommended for the supply’s

isolation. As shown in Figure 38, this assumes that the 2.7 V

system voltage is applied first and that the P1 and P2 gates are

pulled to ground, thus turning on P1 first and then P2. As a

result, VDD of the AD5273 approaches 2.7 V. When the AD5273

setting is found, the factory tester applies the VDD_OTP to both

the VDD and the MOSFETs’ gates, thus turning off P1 and P2.

The OTP command should be executed at this time to program

the AD5273 while the 2.7 V source is protected. Once the fuse

programming is complete, the tester withdraws the VDD_OTP and

the AD5273’s setting is fixed permanently.

Figure 38. OTP Supply Isolated from the 2.7 V Normal Operating Supply

The AD5273 achieves the OTP function through blowing internal

fuses. Users should always apply the recommended OTP

programming voltage at the first fuse programming attempt.

Failure to comply with this requirement can lead to a change in

fuse structures, rendering programming inoperable.

Care should be taken when SCL and SDA are driven from a low

voltage logic controller. Users must ensure that the logic high

level is between 0.7 × VDD and VDD. Refer to the Level Shift for

Different Voltages Operation section.

Poor PCB layout introduces parasitics that can affect fuse program-

ming. Therefore, it is recommended to add a 10 µF tantalum

capacitor in parallel with a 1 nF ceramic capacitor as close as

possible to the VDD pin. The type and value chosen for both capaci-

tors are important. This combination of capacitor values provides a

fast response and larger supply current handling with minimum

supply drop during transients. As a result, these capacitors increase

the OTP programming success by not inhibiting the proper energy

needed to blow the internal fuses. Additionally, C1 minimizes

transient disturbance and low frequency ripple, while C2 reduces

high frequency noise during normal operation.

LOGIC

340

Ω

GND

VDD

AD5273

VDD

0.1µF

APPLIES FOR OTP ONLY

10mF

10kΩ

2.7V

VDD_OTP

P1 = P2 = FDV302P, NDS0610

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