ADF4002BCPZ datasheet(16/21 Pages) AD

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Data Sheet

ADF4002

Rev. D | Page 15 of 20

FUNCTION LATCH

With C2, C1 set to 1, 0, the on-chip function latch is

programmed. Figure 18 shows the input data format for

programming the function latch.

Counter Reset

DB2 (F1) is the counter reset bit. When this bit is set to 1, the

R counter and the N counter are reset. For normal operation,

set this bit to 0. Upon powering up, the F1 bit needs to be

disabled (set to 0). Then, the N counter resumes counting in

close alignment with the R counter (the maximum error is one

prescaler cycle).

Power-Down

DB3 (PD1) and DB21 (PD2) provide programmable power-

down modes. These bits are enabled by the CE pin.

When the CE pin is low, the device is immediately disabled

regardless of the states of the PD2, PD1 bits.

In the programmed asynchronous power-down, the device

powers down immediately after latching a 1 into Bit PD1, with

the condition that Bit PD2 has been loaded with a 0.

In the programmed synchronous power-down, the device

power-down is gated by the charge pump to prevent unwanted

frequency jumps. Once the power-down is enabled by writing

a 1 into Bit PD1 (on condition that a 1 has also been loaded to

Bit PD2), then the device enters power-down on the occurrence

of the next charge pump event.

When a power-down is activated (either in synchronous or

asynchronous mode, including a CE pin activated power-

down), the following events occur:

•

All active dc current paths are removed.

•

The R, N, and timeout counters are forced to their load

state conditions.

•

The charge pump is forced into three-state mode.

•

The digital lock detect circuitry is reset.

•

The RFIN input is debiased.

•

The reference input buffer circuitry is disabled.

•

The input register remains active and capable of loading

and latching data.

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, and M1 on

the ADF4002. Figure 18 shows the truth table.

Fastlock Enable Bit

DB9 of the function latch is the fastlock enable bit. Only when

this is 1 is fastlock enabled.

Fastlock Mode Bit

DB10 of the function latch is the fastlock mode bit. When

fastlock is enabled, this bit determines the fastlock mode to be

used. If the fastlock mode bit is 0, then Fastlock Mode 1 is

selected, and if the fastlock mode bit is 1, then Fastlock Mode 2

is selected.

Fastlock Mode 1

In this mode, the charge pump current is switched to the

contents of Current Setting 2. The device enters fastlock by

having a 1 written to the CP gain bit in the N counter latch. The

device exits fastlock by having a 0 written to the CP gain bit in

the AB counter latch.

Fastlock Mode 2

In this mode, the charge pump current is switched to the

contents of Current Setting 2. The device enters fastlock by

having a 1 written to the CP gain bit in the N counter latch. The

device exits fastlock under the control of the timer counter.

After the timeout period determined by the value in TC4 to

TC1, the CP gain bit in the N counter latch is automatically

reset to 0 and the device reverts to normal mode instead of

fastlock. See Figure 18 for the timeout periods.

Timer Counter Control

The user has the option of programming two charge pump

currents. The intent is to use the Current Setting 1 when the

RF output is stable and the system is in a static state. Current

Setting 2 is meant to be used when the system is dynamic and

in a state of change, that is, when a new output frequency is

programmed.

The normal sequence of events is as follows:

The user initially decides the referred charge pump currents.

For example, the choice can be 2.5 mA as Current Setting 1 and

5 mA as Current Setting 2.

At the same time, the decision must be made as to how long the

secondary current is to stay active before reverting to the

primary current. This is controlled by Timer Counter Control

Bit DB14 to Timer Counter Control Bit DB11 (TC4 to TC1) in

the function latch. See Figure 18 for the truth table.

To program a new output frequency, simply program the N

counter latch with a new value for N. At the same time, the CP

gain bit can be set to 1. This sets the charge pump with the

value in CPI6 to CPI4 for a period of time determined by TC4

to TC1. When this time is up, the charge pump current reverts

to the value set by CPI3 to CPI1. At the same time, the CP gain

bit in the N counter latch is reset to 0 and is ready for the next

time that the user wishes to change the frequency.

Note that there is an enable feature on the timer counter. It is

enabled when Fastlock Mode 2 is chosen by setting the Fastlock

Mode Bit DB10 in the function latch to 1.

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