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ADF4002

Data Sheet

Rev. D | Page 18 of 20

ADuC812 Interface

Figure 22 shows the interface between the ADF4002 and the

ADuC812 MicroConverter®. Because the ADuC812 is based on

an 8051 core, this interface can be used with any 8051-based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4002 needs a

24-bit word. This is accomplished by writing three 8-bit bytes

from the MicroConverter to the device. When the third byte

has been written, bring the LE input high to complete the

transfer.

On first applying power to the ADF4002, it needs four writes

(one each to the initialization latch, function latch, R counter

latch, and N counter latch) for the output to become active.

I/O port lines on the ADuC812 are also used to control power-

down (CE input) and to detect lock (MUXOUT configured as

lock detect and polled by the port input).

When operating in the SPI master mode, the maximum SCLOCK

rate of the ADuC812 is 4 MHz. This means that the maximum

rate at which the output frequency can be changed is 166 kHz.

CLK

DATA

MUXOUT

(LOCK DETECT)

MOSI

SCLOCK

I/O PORTS

ADuC812

ADF4002

Figure 22. ADuC812 to ADF4002 Interface

ADSP-2181 Interface

Figure 23 shows the interface between the ADF4002 and the

ADSP-2181 digital signal processor. The ADF4002 needs a

24-bit serial word for each latch write. The easiest way to accom-

plish this using the ADSP-2181 family is to use the autobuffered

transmit mode of operation with alternate framing. This provides

a means for transmitting an entire block of serial data before an

interrupt is generated. Set up the word length for eight bits and

use three memory locations for each 24-bit word. To program

each 24-bit latch, store the three 8-bit bytes, enable the

autobuffered mode, and then write to the transmit register of

the DSP. This last operation initiates the autobuffer transfer.

CLK

DATA

MUXOUT

(LOCK DETECT)

ADSP-2181

ADF4002

SCLK

I/O FLAGS

TFS

Figure 23. ADSP-2181 to ADF4002 Interface

PCB DESIGN GUIDELINES FOR CHIP SCALE

PACKAGE

The lands on the lead frame chip scale package (CP-20-1) are

rectangular. The printed circuit board pad for these should be

0.1 mm longer than the package land length and 0.05 mm wider

than the package land width. The land should be centered on

the pad. This ensures that the solder joint size is maximized.

The bottom of the lead frame chip scale package has a central

thermal pad.

The thermal pad on the printed circuit board should be at least

as large as this exposed pad. On the printed circuit board, there

should be a clearance of at least 0.25 mm between the thermal

pad and the inner edges of the pad pattern. This ensures that

shorting is avoided.

Thermal vias can be used on the printed circuit board thermal

pad to improve thermal performance of the package. If vias are

used, they should be incorporated into the thermal pad at a

1.2 mm pitch grid. The via diameter should be between 0.3 mm

and 0.33 mm and the via barrel should be plated with 1 oz

copper to plug the via.

The user should connect the printed circuit board thermal pad

to AGND.

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