LMX2624PAPSLASHEM datasheet(32/92 Pages) TI2

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Device 1

Device 2

fOUT1

fOUT2

fOSC

SYNC

fOSC

fOUT1

fOUT2

Figure 6-4. Multi-device Synchronization Using SYNC input

When the SYNC feature is enabled (VCO_PHASE_SYNC = 1), part of the channel divide (IncludedDivide) can

be included in the feedback path. When IncludedDivide is not equal to 1:

• N divider is smaller. Care must be taken not to violate the minimum N divider restriction. Also make use of the

FCAL_HPFD_ADJ register as per phase detector frequency range for valid VCO calibration.

Table 6-11. IncludedDivide With VCO_PHASE_SYNC = 1

OUTx_MUX

CHANNEL DIVIDER

IncludedDivide

OUTA_MUX = OUTB_MUX = 1 ("VCO") OUTA_MUX =

OUTB_MUX = 2 ("Doubler")

Don't Care

1 (bypassed)

All Other Valid Conditions

Divisible by 3

All other values

Div 2

or 3

Divide by

2, 4, 8, 16, 32,

64, 128, 256

RFoutA

RFoutB

Div 2

Charge

Pump

N Divider

Post-R

Divider

Pre-R

Divider

External loop filter

OSCin

Buffer

OSCin

mux

(IncludedDivide)

Figure 6-5. Phase SYNC Diagram

Phase SYNC refers to the process of getting the same phase relationship for every power up cycle and each

time assuming that a given programming procedure is followed. However, there are some adjustments that

can be made to get the most accurate results. As for the consistency of the phase SYNC, the only source

of variation can be if the VCO calibration chooses a different VCO core and capacitor, which can introduce a

bimodal distribution with about 10ps of variation. If this 10ps is not desirable, then the variation can be eliminated

by reading back the VCO core, capcode, and DACISET values and forcing these values to provide the same

calibration settings every time.

6.3.13.2 Categories of Applications for SYNC

The requirements for SYNC depend on certain setup conditions. In cases that the SYNC is not timing critical, the

SYNC can be done through software by toggling the VCO_PHASE_SYNC bit from 0 to 1. Figure 6-6 provides

the different categories. When timing is critical, then SYNC must be done through the pin and the setup and hold

times for the OSCin pin are critical. For timing critical sync (Category 3) ONLY, adhere to the following SYNC Pin

Timing Characteristics for Category 3 SYNC.

Table 6-12. SYNC Pin Timing Characteristics for Category 3 SYNC

Parameter

Description

Min

Max

Unit

fOSC

Input Reference Clock Frequency

MHz

tSETUP

Setup time between SYNC and OSCin rising edges

2.5

tHOLD

Hold time between SYNC and OSCin rising edges

2.5

LMX2624-SP

SNAS849B – DECEMBER 2024 – REVISED SEPTEMBER 2026

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