Circuit Note

CN-0584

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Rev. 0 | 3 of 7

to ADC input mode, a pulse was applied to one of the ADC channel

inputs, and the corresponding DAC channel output was monitored.

The latency from the measured input signal to the DAC output

signal beginning to rise was approximately 250 ns; 50 ns of this

delay is attributed to the internal FPGA data processing, while the

remaining 200 ns of the delay is attributed to ADC data capture and

DAC update.

Figure 4. DAC Output Latency

Analog Input Performance

The analog signal acquisition path of the CN0584 exhibits very high

spurious-free dynamic range (SFDR). Figure 5 shows a 16K point

FFT of the ADC's data at a sample rate of 15 MSPS, with a 1

kHz, ±10 V sinusoidal input signal. The CN0584 achieves 105 dB

of SFDR, dominated by the 3rd harmonic. All other spurs are lower

than 120 dBc across the full 7.5 MHz input frequency range.

Figure 5. CN0584 Analog Input Acquisition Spectrum

Figure 6 shows the same spectrum plot over a frequency range

extending to 1 MHz, showing that no other harmonics or spurs over

-120 dBm are present.

Figure 6. Analog Input Acquisition Spectrum to 1 MHz

Figure 7 shows the input frequency response of the ADC.

Figure 7. ADC Input Frequency Response

Output Filtering

A low pass filter is present at the output of each DAC. Figure 8

shows the frequency response of the filter as measured to 7.5 MHz,

with the ADC output used as the DAC input.

Figure 8. ADC and DAC Filter Composite Response