ST10 datasheet(45/65 Pages) STMICROELECTRONICS

45 / 65 page

ST10C167

45/65

XX.4.8 - External clock drive XTAL1

VDD =5V ± 10%, VSS =0V, TA = -40 to +125°C unless otherwise specified.

Notes 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal.

2. 25MHz is the maximum input frequency when using an external crystal oscillator; however, 50MHz can be applied with an external

clock source.

3. The input clock signal must reach the defined levels VIL and VIH2.

XX.4.9 - Multiplexed bus

VDD =5V ± 10%, VSS = 0V, TA = -40 to +125°C

CL (for Port0, Port1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100pF,

CL (for Port 6, CS) = 100pF

ALE cycle time = 6 TCL + 2tA +tC +tF (120ns at 25MHz CPU clock without wait states)

Symbol

Parameter

fCPU =fXTAL

fCPU =fXTAL /2

fCPU =fXTAL *N

N = 1.5/2,/2.5/3/4/5

Unit

Min.

Max.

Min.

Max.

Min.

Max.

tOSC

Oscillator period

40 1

1000

20 2

500

40 * N

100 * N

High time

18 3

–

6 3

–

10 3

–ns

Low time

18 3

–

6 3

–

10 3

–ns

Rise time

–

10 3

–

6 3

–

10 3

Fall time

–

10 3

–

6 3

–

10 3

Figure 13 : External clock drive XTAL1

Table 18 : Multiplexed bus characteristics

Symbol

Parameter

Max. CPU Clock

= 25MHz

Variable CPU Clock

1/2TCL = 1 to 25MHz

Unit

Min.

Max.

Min.

Max.

ALE high time

10 + tA

–

TCL - 10 + tA

–ns

Address setup to ALE

4 + tA

–

TCL - 16+ tA

–ns

Address hold after ALE

10 + tA

–

TCL - 10 + tA

–ns

ALE falling edge to RD, WR

(with RW-delay)

10 + tA

–

TCL - 10 + tA

–ns

ALE falling edge to RD, WR (no

RW-delay)

-10 + tA

–

-10 + tA

–ns

VIL

tOSC

VIH2

XX - ELECTRICAL CHARACTERISTICS (continued)

ST10 Scheda tecnica(PDF) 45 Page - STMicroelectronics

ST10 Scheda tecnica(HTML) 45 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

Scheda tecnica Scarica

Link URL