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ST92141 Scheda tecnica(PDF) 133 Page - STMicroelectronics

Il numero della parte ST92141
Spiegazioni elettronici  8/16-BIT MCU FOR 3-PHASE AC MOTOR CONTROL
PDF  179 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

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ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont’d)
DEAD TIME GENERATOR REGISTER (DTG)
R254 - Read/Write
Register Page: 48
Reset Value: 0011 1111 (3Fh)
Bit 7:6 = Reserved.
Bit 5:0 = DTG[5:0]
Dead time generator value (N).
The delay is N x INTCLK period multiplied by 2.
If N = 0 the delay is 0.
IMC INTERRUPT VECTOR REGISTER (IMCIVR)
R255 - Read/Write
Register Page: 48
Reset Value: undefined (17h)
Bit 7:4 = V[3:0]:
Interrupt Vector Base Address.
User programmable interrupt vector bits.
The most significant nibble of the interrupt vector
address is given by V[3:0]. The other nibble is giv-
en by W[3:0] where W[0] is forced to ‘0’ and W[3:1]
are set by hardware according to the Table 26 In-
terrupt Source Address.
Table 26. Interrupt Source Address
Bit 3 = NMI:
Non Maskable Interrupt pending bit.
This bit is set by hardware when an NMI event oc-
curs and the NMIE bit = 1. The NMI bit can be
cleared by software. It cannot be set by software.
As long as this bit is ‘1’ the NMI signal to ST9 is
kept active (high level).
0: No NMI pending
1: NMI pending
Note: As long as the external NMI signal is active
the NMI bit can not be reset.
Bit 2:0 = PL[2:0]: Priority level for the peripheral
interrupt.
70
-
-
DTG5 DTG4 DTG3 DTG2 DTG1 DTG0
70
V3
V2
V1
V0
NMI
PL2
PL1
PL0
W[3:1]
Interrupt Source
000
ADT Data transfer
001
ZPC Zero event of PWM counter
010
CM0 PWM counter Compare 0
011
CPT Tacho capture
100
CPU Compare U
101
CPV Compare V
110
CPW Compare W
111
OTC Tacho counter overflow
9



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