RMLD232UAW datasheet(8/50 Pages) EMLSI

8 / 50 page

Rev 0.7

64Mb Low Power DDR SDRAM

Advanced

Extended Mode Register Set (EMRS)

The extended mode register is designed to support partial array self refresh or driver strength. EMRS cycle is not mandatory and the

EMRS command needs to be issued only when either PASR or DS is used. The defalt state without EMRS command issued is +85

all 4 banks refreshed and the half size of driver strength. The extended mode register is written by asserting low on CS, RAS,

CAS, WE and high on BA1, low on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into

the extended mode register). The state of address pins A0 ~ A10 in the same cycle as CS, RAS, CAS and WE going low is written in

the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. Even if the

power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed

with the same command and four clock cycles. But this command must be issued only when all banks are in the idle state. A0 ~ A2

are used for partial array self refresh and A5 ~ A6 are used for driver strength. “High” on BA1 and “Low” on BA0 are used for EMRS.

All the other address pins except A0, A1, A2, A5, A6, BA1, BA0 must be set to low for proper EMRS operation. Refer to the table for

specific codes.

Extended MRS for PASR(Partial Array Self Refresh) & DS &

TCSR(Internal Temperature Compensated Self Refresh)

BA1

BA0

A10

PASR

Driver Strength

Full

1/2 (default)

1/4

1/8

Address Bus

Mode Register

Inernal TCSR

Self refresh cycle is controlled

automatically by internal tem-

perature sensor and control cir-

cuit according to the four

temperature ; Max 15

, Max

Max 70

Max 85

PASR

Size of Refreshed

Array

Four Banks (default)

Two Banks

(Bank 0,1)

One Bank

(Bank 0)

Reserved

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