RMLD232UAW datasheet(22/50 Pages) EMLSI

22 / 50 page

Rev 0.7

64Mb Low Power DDR SDRAM

Advanced

Auto Refresh & Self Refresh

Auto Refresh

An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the clock(CK).

All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external address

pins is required once this cycle has started because of the internal address counter. When the refresh cycle has completed, all banks

will be in the idle state. A delay between the auto refresh command and the next activate command or subsequent auto refresh com-

mand must be greater than or equal to the tARFC(min).

Self Refresh

A Self Refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once

the self Refresh command is initiated, CKE must be held low to keep the device in Self Refresh mode. After 1 clock cycle from the self

refresh command, all of the external control signals including sysem clock(CK, CK) can be disabled except CKE. The clock is inter-

nally disabled during Self Refresh operation to reduce power. To exit the Self Refresh mode, supply stable clock input before return-

ing CKE high, assert deselect or NOP command and then assert CKE high. In case that the system uses burst auto refresh during

normal operation, it is recommended to use burst 8192 auto refresh cycle immediately before entering self refresh mode and after

exiting in self refresh mode. On the other hand, if the system uses the distributed auto refresh, the system only has to keep the

refresh duty cycle.

NOP

CKE

Active

PRE

Auto

Refresh

CMD

CKE = High

tRP

tARFC(min)

Figure.16 Auto refresh timing

Self

Refresh

tIS

Stable Clock

tSRFX(min)

tIS

Figure.17 Self refresh timing

Command

RMLD232UAW Scheda tecnica(PDF) 22 Page - Emerging Memory & Logic Solutions Inc