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STE100 Scheda tecnica(PDF) 60 Page - STMicroelectronics |
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STE100 Scheda tecnica(HTML) 60 Page - STMicroelectronics |
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60 / 66 page ![]() STE10/100 60/66 8.1 Timing Specifications Table 19. PCI Clock Specifications Figure 16. PCI Clock Waveform Table 20. X1 Specifications Symbol Parameter Test Condition Min. Typ. Max. Units Tc Clock Cycle Time 30 50 ns Th Clock High Time 11 -- ns Tl Clock Low Time 11 -- ns Clock Slew Rate 1 4 V/ns Symbol Parameter Test Condition Min. Typ. Max. Units TX1d X1 Duty Cycle 45 50 55 % TX1p X1 Period 30 ns TX1t X1 Tolerance PPM Table 21. PCI Timing Symbol Parameter Test Condition Min. Typ. Max. Units Tval Clock to Signal Valid Delay (bussed signals) 211 ns Tval(ptp) Clock to Signal Valid Delay (point to point) 211 ns Ton Float to Active Delay 2 ns Toff Active to Float Delay 28 ns 1.5V 2.4V 0.4V Th Tc 2.0V Tl 0.8V 2V pick to pick |
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