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LFSC Scheda tecnica(PDF) 29 Page - Lattice Semiconductor

Il numero della parte LFSC
Spiegazioni elettronici  LatticeSC/M Family Data Sheet
PDF  237 Pages
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Produttore elettronici  LATTICE [Lattice Semiconductor]
Homepage  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LFSC Scheda tecnica(HTML) 29 Page - Lattice Semiconductor

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2-25
Architecture
Lattice Semiconductor
LatticeSC/M Family Data Sheet
Figure 2-26. LatticeSC Banks
Table 2-7. Maximum Number of I/Os Per Bank in LatticeSC Family
The LatticeSC devices contain three types of PURESPEED I/O buffers:
1.
Left and Right Sides (Banks 2, 3, 6 and 7)
These buffers can support LVCMOS standards up to 2.5V. A differential output driver (for LVDS, RSDS, and
HYPT) is provided on all primary PIO pairs (A and B) and differential receivers are available on all pairs. Com-
plimentary drivers are available. Adaptive input logic is available on PIOs A or C.
2.
Top Side (Bank 1)
These buffers can support LVCMOS standards up to 3.3V, including PCI33, PCI-X33 and SSTL-33. Differential
receivers are provided on all PIO pairs but differential drivers for LVDS, RSDS, and HYPT are not available.
Adaptive input logic is not available on this side. Complimentary output drivers are available.
Device
LFSC/M15
LFSC/M25
LFSC/M40
LFSC/M80
LFSC/M115
Bank1
104
80
136
80
136
Bank2
28
36
60
96
136
Bank3
60
84
96
132
156
Bank4
72
100
124
184
208
Bank5
72
100
124
184
208
Bank6
60
84
96
132
156
Bank7
28
36
60
96
136
Note: Not all the I/Os of the Banks are available in all the packages
VREF1[7]
GND
VCCIO7
VTT7
VREF2[7]
VREF1[6]
GND
VCCIO6
VTT6
VREF2[6]
VREF1[2]
GND
VCCIO2
VTT2
VREF2[2]
VREF1[3]
GND
VCCIO3
VTT[3]
VREF2[3]
Bank 4
SERDES
SERDES
Bank 5
Bank 1



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