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ST72F321BAR6TCRE Scheda tecnica(PDF) 44 Page - STMicroelectronics |
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ST72F321BAR6TCRE Scheda tecnica(HTML) 44 Page - STMicroelectronics |
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44 / 247 page ![]() Supply, reset and clock management ST72321Bxxx-Auto 44/247 6 Supply, reset and clock management 6.1 Introduction The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 9. For more details, refer to the dedicated parametric section. 6.2 Main features ● Optional PLL for multiplying the frequency by 2 (not to be used with internal RC oscillator) ● Reset Sequence Manager (RSM) ● Multi-oscillator Clock Management (MO) – 5 crystal/ceramic resonator oscillators – 1 internal RC oscillator ● System Integrity Management (SI) – Main supply low voltage detection (LVD) – Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main supply or the EVD pin Figure 9. Clock, reset and supply block diagram LOW VOLTAGE DETECTOR (LVD) fOSC2 AUXILIARY VOLTAGE DETECTOR (AVD) MULTI- OSCILLATOR (MO) OSC1 RESET VSS EVD VDD RESET SEQUENCE MANAGER (RSM) OSC2 MAIN CLOCK AVD Interrupt Request CONTROLLER PLL SYSTEM INTEGRITY MANAGEMENT WATCHDOG SICSR TIMER (WDG) WITH REAL-TIME CLOCK (MCC/RTC) AVD AVD AVD LVD RF IE WDG RF 0 1 fOSC (option) 0 S F fCPU 00 |
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