PSD4235G2-12UI datasheet(6/89 Pages) STMICROELECTRONICS

6 / 89 page

PSD4235G2

6/89

Figure 3. TQFP Connections

In-Application Programming (IAP)

Two independent Flash memory arrays are includ-

ed so that the MCU can execute code from one

while erasing and programming the other. Robust

product firmware updates in the filed are possible

over any communication channel (CAN, Ethernet,

UART, J1850, etc) using this unique architecture.

Designers are relieved of these problems:

Simultaneous read and write to Flash memo-

ry. How can the MCU program the same memory

from which it executing code? It cannot. The PSD

allows the MCU to operate the two Flash memory

blocks concurrently, reading code from one while

erasing and programming the other during IAP.

Complex memory mapping. How can I map

these two memories efficiently? A programmable

Decode PLD (DPLD) is embedded in the PSD.

The concurrent PSD memories can be mapped

anywhere in MCU address space, segment by

segment with extermely high address resolution.

As an option, the secondary Flash memory can be

swapped out of the system memory map when

IAP is complete. A built-in page register breaks the

MCU address limit.

Separate Program and Data space. How can I

write to Flash memory while it resides in Program

space

during

field

firmware

updates?

80C51XA will not allow it. The PSD provides

means to reclassify Flash memory as Data space

during IAP, then back to Program space when

complete.

60 CNTL1

59 CNTL0

58 PA7

57 PA6

56 PA5

55 PA4

54 PA3

53 PA2

52 PA1

51 PA0

50 GND

49 GND

48 PC7

47 PC6

46 PC5

45 PC4

44 PC3

43 PC2

42 PC1

41 PC0

PD2

PD3

AD0

AD1

AD2

AD3

AD4

GND

VCC

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AI04943

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