R32C121 datasheet(78/113 Pages) RENESAS

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REJ03B0237-0050 Rev.0.50 Jul 31, 2008

Page 78 of 111

Under development

Preliminary Specification

This is a preliminary specification and is subject to change.

R32C/121 Group

5. Electrical Characteristics

Note:

The device is operationally guaranteed under these operating conditions.

Figure 5.1

Clock Cycle Time

Table 5.5

Operating Conditions (4)

(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta =Topr, unless otherwise noted) (1)

Symbol

Characteristic

Value

Unit

Min.

Typ.

Max.

f(XIN)

Main clock oscillator frequency

MHz

f(XRef)

Reference clock frequency

MHz

f(PLL)

PLL clock oscillator frequency

144

MHz

f(Base)

Base clock frequency

MHz

tc(Base)

Base clock cycle time

15.625

f(CPU)

CPU operating frequency

MHz

tc(CPU)

CPU clock cycle time

15.625

f(BCLK)

Peripheral bus clock operating frequency

MHz

tc(BCLK)

Peripheral bus clock cycle time

31.25

f(PER)

Peripheral clock source frequency

MHz

f(XCIN)

Sub clock oscillator frequency

32.768

kHz

Base clock

(Internal signal)

t c(Base)

Peripheral bus clock

(Internal signal)

t c(BCLK)

CPU clock

(Internal signal)

t c(CPU)

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