R32C121 datasheet(16/113 Pages) RENESAS

16 / 113 page

REJ03B0237-0050 Rev.0.50 Jul 31, 2008

Page 16 of 111

Under development

Preliminary Specification

This is a preliminary specification and is subject to change.

R32C/121 Group

2. Central Processing Unit (CPU)

2.1.8.5

This flag selects a register bank. It indicates 0 when the register bank 0 is selected, and 1 when the

2.1.8.6

Overflow Flag (O flag)

This flag becomes 1 if an operation results in an overflow; in all other cases, this flag becomes 0.

2.1.8.7

Interrupt Enable Flag (I flag)

This flag enables a maskable interrupt. It indicates 0 when an interrupt is disabled, and 1 when an

interrupt is enabled. Once an interrupt is accepted, the flag is set to 0.

2.1.8.8

Stack Pointer Select Flag (U flag)

This flag indicates 0 when the interrupt stack pointer (ISP) is selected, and 1 when the user stack

pointer (USP) is selected.

It is set to 0 when a hardware interrupt is accepted or the INT instruction whose software interrupt

number is 0 to 127 is executed.

2.1.8.9

Floating-point Underflow Flag (FU flag)

This flag becomes 1 if a floating point operation results in an underflow; in all other cases, this flag

becomes 0. It also becomes 1 when the operand has invalid numbers (subnormal numbers).

2.1.8.10

Floating-point Overflow Flag (FO flag)

This flag becomes 1 if a floating point operation results in an overflow; in all other cases, this flag

becomes 0. It also becomes 1 when the operand has invalid numbers (subnormal numbers).

2.1.8.11

Processor Interrupt Priority Level (IPL)

The 3-bit processor interrupt priority level (IPL) specifies eight processor interrupt priority levels from 0

to 7. If a requested interrupt's priority level is higher than the processor interrupt priority level (IPL), this

interrupt is enabled.

If the processor interrupt priority level (IPL) is set to 111b (level 7), any interrupt is disabled.

2.1.8.12

Fixed-point Designation Bit (DP bit)

This bit designates a fixed point. It also designates which part of the multiplication result should be

taken. It is used for MULX instruction.

2.1.8.13

Floating-point Rounding Mode (RND)

The 2-bit floating point rounding mode designates a rounding mode for the operation result.

2.1.8.14

Reserved

The fields are written with 0. The read value is undefined.

R32C121 Scheda tecnica(PDF) 16 Page - Renesas Technology Corp

R32C121 Scheda tecnica(HTML) 16 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL