4513 datasheet(31/97 Pages) RENESAS

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4513/4514 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Table 10 Timer control registers

W21

Stop (state initialized)

Operating

Instruction clock divided by 4

Instruction clock divided by 16

Stop (state retained)

Operating

Count start synchronous circuit not selected

Count start synchronous circuit selected

Prescaler control bit

Prescaler dividing ratio selection bit

Timer 1 control bit

Timer 1 count start synchronous circuit

control bit

Stop (state retained)

Operating

This bit has no function, but read/write is enabled.

Count source

Timer 1 underflow signal

Prescaler output

CNTR0 input

16 bit timer (WDT) underflow signal

Timer 2 control bit

Not used

Timer 2 count source selection bits

W20

W13

W12

W11

W10

W23

W22

W21

W20

W33

W32

W31

W30

W43

W42

W41

W40

W63

W62

W61

W60

Timer control register W1

R/W

at RAM back-up : 00002

at reset : 00002

R/W

at RAM back-up : 00002

at reset : 00002

Timer control register W2

R/W

at RAM back-up : state retained

at reset : 00002

W31

Stop (state retained)

Operating

Count start synchronous circuit not selected

Count start synchronous circuit selected

Count source

Timer 2 underflow signal

Prescaler output

Not available

Timer 3 control bit

Timer 3 count start synchronous circuit

control bit

Timer 3 count source selection bits

W30

Timer control register W3

R/W

at RAM back-up : state retained

at reset : 00002

W41

Stop (state retained)

Operating

This bit has no function, but read/write is enabled.

Count source

Timer 3 underflow signal

Prescaler output

CNTR1 input

Not available

Timer 4 control bit

Not used

Timer 4 count source selection bits

W40

Timer control register W4

R/W

at RAM back-up : state retained

at reset : 00002

Timer 3 underflow signal output divided by 2

CNTR1 output control by timer 4 underflow signal divided by 2

D7(I/O)/CNTR1 input

CNTR1 (I/O)/D7(input)

Timer 1 underflow signal output divided by 2

CNTR0 output control by timer 2 underflow signal divided by 2

D6(I/O)/CNTR0 input

CNTR0 (I/O)/D6(input)

CNTR1 output control bit

D7/CNTR1 function selection bit

CNTR0 output control bit

D6/CNTR0 output control bit

Timer control register W6

R/W

at RAM back-up : state retained

at reset : 00002

Note: “R” represents read enabled, and “W” represents write enabled.

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