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SH7619 Scheda tecnica(PDF) 86 Page - Renesas Technology Corp |
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SH7619 Scheda tecnica(HTML) 86 Page - Renesas Technology Corp |
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86 / 836 page ![]() Section 2 CPU Rev. 5.00 Mar. 15, 2007 Page 48 of 794 REJ09B0237-0500 • Shift Instructions Instruction Operation Code Execution Cycles T Bit ROTL Rn T ← Rn ← MSB 0100nnnn00000100 1 MSB ROTR Rn LSB → Rn → T 0100nnnn00000101 1 LSB ROTCL Rn T ← Rn ← T 0100nnnn00100100 1 MSB ROTCR Rn T → Rn → T 0100nnnn00100101 1 LSB SHAL Rn T ← Rn ← 0 0100nnnn00100000 1 MSB SHAR Rn MSB → Rn → T 0100nnnn00100001 1 LSB SHLL Rn T ← Rn ← 0 0100nnnn00000000 1 MSB SHLR Rn 0 → Rn → T 0100nnnn00000001 1 LSB SHLL2 Rn Rn << 2 → Rn 0100nnnn00001000 1 SHLR2 Rn Rn >> 2 → Rn 0100nnnn00001001 1 SHLL8 Rn Rn << 8 → Rn 0100nnnn00011000 1 SHLR8 Rn Rn >> 8 → Rn 0100nnnn00011001 1 SHLL16 Rn Rn << 16 → Rn 0100nnnn00101000 1 SHLR16 Rn Rn >> 16 → Rn 0100nnnn00101001 1 • Branch Instructions Instruction Operation Code Execution Cycles T Bit BF label If T = 0, disp × 2 + PC → PC; if T = 1, nop 10001011dddddddd 3/1* BF/S label Delayed branch, if T = 0, disp × 2 + PC → PC; if T = 1, nop 10001111dddddddd 2/1* BT label If T = 1, disp × 2 + PC → PC; if T = 0, nop 10001001dddddddd 3/1* BT/S label Delayed branch, if T = 1, disp × 2 + PC → PC; if T = 0, nop 10001101dddddddd 2/1* |
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