SH7619 datasheet(21/836 Pages) RENESAS

21 / 836 page

Rev. 5.00 Mar. 15, 2007 Page xxi of xxxviii

Section 24 List of Registers .................................................................................675

24.1

24.2

Register Bits...................................................................................................................... 684

24.3

Section 25 Electrical Characteristics ...................................................................713

25.1

Absolute Maximum Ratings ............................................................................................. 713

25.2

Power-On and Power-Off Order ....................................................................................... 714

25.3

DC Characteristics ............................................................................................................ 716

25.4

AC Characteristics ............................................................................................................ 718

25.4.1

Clock Timing .................................................................................................... 719

25.4.2

Control Signal Timing ...................................................................................... 723

25.4.3

AC Bus Timing................................................................................................. 725

25.4.4

Basic Timing..................................................................................................... 727

25.4.5

Synchronous DRAM Timing ............................................................................ 733

25.4.6

PCMCIA Timing .............................................................................................. 750

25.4.7

DMAC Signal Timing....................................................................................... 754

25.4.8

SCIF Timing ..................................................................................................... 755

25.4.9

SIOF Module Signal Timing ............................................................................ 756

25.4.10

Port Timing ....................................................................................................... 760

25.4.11

HIF Timing ....................................................................................................... 761

25.4.12

EtherC Timing .................................................................................................. 764

25.4.13

H-UDI Related Pin Timing ............................................................................... 767

25.4.14

AC Characteristic Test Conditions ................................................................... 769

25.5

Physical Layer Ttransceiver (PHY) Characteristics (Reference Values).......................... 770

Appendix..............................................................................................................771

Port States in Each Pin State ............................................................................................. 771

Product Code Lineup ........................................................................................................ 776

Package Dimensions ......................................................................................................... 777

Main Revisions and Additions in this Edition .....................................................779

Index ....................................................................................................................787

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