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HD6432137SW Scheda tecnica(PDF) 97 Page - Renesas Technology Corp |
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HD6432137SW Scheda tecnica(HTML) 97 Page - Renesas Technology Corp |
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97 / 1061 page  Section 2 CPU Rev. 4.00 Jun 06, 2006 page 43 of 1004 REJ09B0301-0400 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Addressing Modes Function Instruction MOV BWL BWL BWL BWL BWL BWL B BWL — BWL — ——— POP, PUSH ————— —————— —— WL LDM* 3, STM*3 ————— —————— —— L Data transfer MOVFPE* 1, MOVTPE* 1 ————— —— B ——— ——— ADD, CMP BWL BWL ——— —————— ——— SUB WL BWL ——— —————— ——— ADDX, SUBX B B ——— —————— ——— ADDS, SUBS — L ——— —————— ——— INC, DEC — BWL ——— —————— ——— DAA, DAS — B ——— —————— ——— MULXU, DIVXU — BW ——— —————— ——— MULXS, DIVXS — BW ——— —————— ——— NEG — BWL ——— —————— ——— EXTU, EXTS — WL ——— —————— ——— Arithmetic operations TAS* 2 —— B —— —————— ——— AND, OR, XOR BWL BWL ——— —————— ——— Logic operations NOT — BWL ——— —————— ——— Shift — BWL ——— —————— ——— Bit manipulation — BB —— — BB — B — ——— Bcc, BSR ————— ————— —— JMP, JSR ————— ——— —— — — Branch RTS ————— —————— —— TRAPA ————— —————— —— RTE ————— —————— —— SLEEP ————— —————— —— LDC B B WWW W — W — W — ——— STC — B WWW W — W — W — ——— ANDC, ORC, XORC B ———— —————— ——— System control NOP ————— —————— —— Block data transfer ————— —————— —— BW Legend: B: Byte W: Word L: Longword Notes: 1. Cannot be used in the H8S/2138 Group or H8S/2134 Group. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 3. Only registers ER0 to ER6 should be used when using the STM/LDM instruction. |
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