HD6432137SW datasheet(25/1061 Pages) RENESAS

25 / 1061 page

Rev. 4.00 Jun 06, 2006 page xxv of liv

12.6.4 Contention between Compare-Matches A and B ................................................. 338

12.6.5 Switching of Internal Clocks and TCNT Operation............................................. 338

Section 13 Timer Connection [H8S/2138 Group]...................................................... 341

13.1

Overview........................................................................................................................... 341

13.1.1 Features................................................................................................................ 341

13.1.2 Block Diagram ..................................................................................................... 342

13.1.3 Input and Output Pins .......................................................................................... 343

13.1.4 Register Configuration......................................................................................... 344

13.2

Register Descriptions ........................................................................................................ 344

13.2.1 Timer Connection Register I (TCONRI) ............................................................. 344

13.2.2 Timer Connection Register O (TCONRO) .......................................................... 347

13.2.3 Timer Connection Register S (TCONRS)............................................................ 349

13.2.4 Edge Sense Register (SEDGR) ............................................................................ 351

13.2.5 Module Stop Control Register (MSTPCR) .......................................................... 354

13.3

Operation .......................................................................................................................... 355

13.3.1 PWM Decoding (PDC Signal Generation) .......................................................... 355

13.3.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) ..................... 357

13.3.3 Measurement of 8-Bit Timer Divided Waveform Period .................................... 358

13.3.4 IHI Signal and 2fH Modification ......................................................................... 360

13.3.5 IVI Signal Fall Modification and IHI Synchronization ....................................... 362

13.3.6 Internal Synchronization Signal Generation

(IHG/IVG/CL4 Signal Generation) ..................................................................... 364

13.3.7 HSYNCO Output ................................................................................................. 367

13.3.8 VSYNCO Output ................................................................................................. 368

13.3.9 CBLANK Output ................................................................................................. 369

Section 14 Watchdog Timer (WDT).............................................................................. 371

14.1

Overview........................................................................................................................... 371

14.1.1 Features................................................................................................................ 371

14.1.2 Block Diagram ..................................................................................................... 372

14.1.3 Pin Configuration................................................................................................. 374

14.1.4 Register Configuration......................................................................................... 374

14.2

Register Descriptions ........................................................................................................ 375

14.2.1 Timer Counter (TCNT)........................................................................................ 375

14.2.2 Timer Control/Status Register (TCSR) ................................................................ 376

14.2.3 System Control Register (SYSCR) ...................................................................... 379

14.2.4 Notes on Register Access..................................................................................... 380

14.3

Operation .......................................................................................................................... 381

14.3.1 Watchdog Timer Operation ................................................................................. 381

14.3.2 Interval Timer Operation ..................................................................................... 382

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