HD6432142 datasheet(354/1177 Pages) RENESAS

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Section 11 16-Bit Free-Running Timer

Rev. 4.00 Sep 27, 2006 page 310 of 1130

REJ09B0327-0400

11.1.4

Table 11.2 lists the registers of the free-running timer module.

Table 11.2

Name

Abbreviation

R/W

Initial Value

Address*

Timer interrupt enable register

TIER

R/W

H'01

H'FF90

Timer control/status register

TCSR

R/(W)*

H'00

H'FF91

Free-running counter

FRC

R/W

H'0000

H'FF92

Output compare register A

OCRA

R/W

H'FFFF

H'FF94*

Output compare register B

OCRB

R/W

H'FFFF

H'FF94*

Timer control register

TCR

R/W

H'00

H'FF96

Timer output compare control

TOCR

R/W

H'00

H'FF97

Input capture register A

ICRA

H'0000

H'FF98*

Input capture register B

ICRB

H'0000

H'FF9A*

Input capture register C

ICRC

H'0000

H'FF9C*

Input capture register D

ICRD

H'0000

H'FF9E

Output compare register AR

OCRAR

R/W

H'FFFF

H'FF98*

Output compare register AF

OCRAF

R/W

H'FFFF

H'FF9A*

Output compare register DM

OCRDM

R/W

H'0000

H'FF9C*

Module stop control register

MSTPCRH

R/W

H'3F

H'FF86

MSTPCRL

R/W

H'FF

H'FF87

Notes: 1. Lower 16 bits of the address.

2. Bits 7 to 1 are read-only; only 0 can be written to clear the flags.

Bit 0 is readable/writable.

3. OCRA and OCRB share the same address. Access is controlled by the OCRS

bit in TOCR.

4. ICRA, ICRB, and ICRC share the same addresses with OCRAR, OCRAF, and

OCRDM. Access is controlled by the ICRS bit in TOCR.

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