HD6432142 datasheet(15/1177 Pages) RENESAS

15 / 1177 page

Rev. 4.00 Sep 27, 2006 page xv of xliv

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23.6.1 Boot Mode

705

Description amended

H'(FF)E088 and above

23.7.2 Program-Verify

Mode

Figure 23.12

Program/Program-Verify

Flowcharts

710

Note

*6 added to figure 23.12

Start

End of programming

End sub

Set SWE bit in FLMCR1

Wait (x)

µs

n = 1

m = 0

Sub-routine-call

See Note 7 for pulse width

Note 7: Write Pulse Width

Start of programming

Sub-routine write pulse

Set PSU bit in FLMCR1

Enable WDT

Set P bit in FLMCR1

Wait (y)

µs

Clear P bit in FLMCR1

Wait (z1)

µs, (z2) µs or (z3) µs

Clear PSU bit in FLMCR2

Wait (

α) µs

Disable WDT

Wait (

β) µs

Write pulse application subroutine

Wait (

γ) µs

Wait (

ε) µs

Wait (

η) µs

Set PV bit in FLMCR1

H'FF dummy write to verify address

Read verify data

Program data =

verify data?

Transfer additional program data

to additional program data area

Additional program data computation

Clear PV bit in FLMCR1

Clear SWE bit in FLMCR1

m = 1

End of 128-byte

data verification?

m = 0?

Increment address

Programming failure

Write 128-byte data in RAM reprogram data

area consecutively to flash memory

Write pulse

(z1)

µs or (z2) µs

RAM

Program data storage

area (128 bytes)

Reprogram data storage

area (128 bytes)

Store 128-byte program data in program

data area and reprogram data area

Number of Writes n

...

998

999

1000

Write Time (z*6)

µsec

...

Reprogram data computation

Transfer reprogram data to reprogram data area *4

≥ n?

Write 128-byte data in additional program data

area in RAM consecutively to flash memory

Additional write pulse (z3)

µs

Wait (

θ) µs

Note: Use a (z3)

µs write pulse for additional

programming.

Additional program data

storage area (128 kbytes)

Perform programming in the erased state.

Do not perform additional programming

on previously programmed addresses.

← n + 1

≥ 1000?

Clear SWE bit in FLMCR1

Wait (

θ) µs

≥ n?

23.10.4 Memory Read

Mode

Figure 23.17 Timing

Waveforms when

Entering Another Mode

from Memory Read

Mode

721

Figure 23.17 amended

FA17 to FA0

FO7 to FO0

H'XX

Other mode command write

twep

tceh

tdh

tds

tces

Data

Memory read mode

Address stable

tnxtc

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