HD6432142 datasheet(463/1177 Pages) RENESAS

Il numero della parte	HD6432142

Spiegazioni elettronici	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1177 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Section 14 Watchdog Timer (WDT)

Rev. 4.00 Sep 27, 2006 page 419 of 1130

REJ09B0327-0400

14.3.4

RESO

RESO Signal Output Timing

When TCNT overflows in watchdog timer mode, the OVF bit is set to 1 in TCSR. If the RST/

NMI

bit is 1 at this time, an internal reset signal is generated for the entire chip, and at the same time a

low-level signal is output from the

RESO pin. The timing is shown in figure 14.6.

TCNT

H'FF

H'00

132 states

518 states

Overflow signal

(internal signal)

OVF

RESO signal

Internal reset

signal

Figure 14.6

RESO

RESO Signal Output Timing

14.4

Interrupts

During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).

The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be

cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is selected in

watchdog timer mode, an overflow generates an NMI interrupt request.

HD6432142 Scheda tecnica(PDF) 463 Page - Renesas Technology Corp