HD6432142 datasheet(577/1177 Pages) RENESAS

Il numero della parte	HD6432142

Spiegazioni elettronici	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1177 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Section 16 I

2C Bus Interface [Option]

Rev. 4.00 Sep 27, 2006 page 533 of 1130

REJ09B0327-0400

16.3.6

IRIC Setting Timing and SCL Control

The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the

FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is

automatically held low after one frame has been transferred; this timing is synchronized with the

internal clock. Figure 16.12 shows the IRIC set timing and SCL control.

(a) When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait)

SCL

SDA

IRIC

User processing

Clear IRIC

Write to ICDR (transmit)

or read ICDR (receive)

(b) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted)

SCL

SDA

IRIC

User processing

Clear

IRIC

Clear

IRIC

Write to ICDR (transmit)

or read ICDR (receive)

SCL

SDA

IRIC

User processing

Clear IRIC

Write to ICDR (transmit)

or read ICDR (receive)

Figure 16.12 IRIC Setting Timing and SCL Control

HD6432142 Scheda tecnica(PDF) 577 Page - Renesas Technology Corp