HD6432142 datasheet(585/1177 Pages) RENESAS

585 / 1177 page

Section 16 I

2C Bus Interface [Option]

Rev. 4.00 Sep 27, 2006 page 541 of 1130

REJ09B0327-0400

16.3.11

Initialization of Internal State

The IIC has a function for forcible initialization of its internal state if a deadlock occurs during

communication.

Initialization is executed by (1) setting bits CLR3 to CLR0 in the DDCSWR register or (2)

clearing the ICE bit. For details of settings for bits CLR3 to CLR0, see section 16.2.8, DDC

Switch Register (DDCSWR).

Scope of Initialization:

The initialization executed by this function covers the following items:

• TDRE and RDRF internal flags

• Transmit/receive sequencer and internal operating clock counter

• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data

output, etc.)

The following items are not initialized:

• Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, STCR)

• Internal latches used to retain register read information for setting/clearing flags in the ICMR,

ICCR, ICSR, and DDCSWR registers

• The value of the ICMR register bit counter (BC2 to BC0)

• Generated interrupt sources (interrupt sources transferred to the interrupt controller)

Notes on Initialization:

• Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be

taken as necessary.

• Basically, other register flags are not cleared either, and so flag clearing measures must be

taken as necessary.

• When initialization is performed by means of the DDCSWR register, the write data for bits

CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written

to simultaneously using an MOV instruction. Do not use a bit-manipulation instruction such as

BCLR. Similarly, when clearing is required again, all the bits must be written to

simultaneously in accordance with the setting.

• If a flag clearing setting is made during transmission/reception, the IIC module will stop

transmitting/receiving at that point and the SCL and SDA pins will be released. When

transmission/reception is started again, register initialization, etc., must be carried out as

necessary to enable correct communication as a system.

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