HD6432142 datasheet(781/1177 Pages) RENESAS

781 / 1177 page

Section 24 Clock Pulse Generator

Rev. 4.00 Sep 27, 2006 page 737 of 1130

REJ09B0327-0400

External Clock

The external clock signal should have the same frequency as the system clock (

φ).

Table 24.4 and figure 24.6 show the input conditions for the external clock.

Table 24.4

External Clock Input Conditions

CC = 2.7 to 5.5 V

CC = 5.0 V ±10%

Item

Symbol

Min

Max

Min

Max

Unit

Test Conditions

External clock

input low pulse

width

EXL

—

Figure 24.6

External clock

input high pulse

width

EXH

—

External clock

rise time

EXr

—

5ns

External clock

fall time

EXf

—

5ns

0.4

0.6

0.4

0.6

cyc

φ ≥ 5 MHz Figure 26.5

Clock low

pulse width

—

φ < 5 MHz

0.4

0.6

0.4

0.6

cyc

φ ≥ 5 MHz

Clock high

pulse width

—

φ < 5 MHz

tEXH

tEXL

tEXr

tEXf

VCC × 0.5

EXTAL

Figure 24.6 External Clock Input Timing

Table 24.5 shows the external clock output settling delay time, and figure 24.7 shows the external

clock output settling delay timing. The oscillator and duty adjustment circuit have a function for

adjusting the waveform of the external clock input at the EXTAL pin. When the prescribed clock

signal is input at the EXTAL pin, internal clock signal output is fixed after the elapse of the

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