HD6432142 datasheet(804/1177 Pages) RENESAS

Il numero della parte	HD6432142

Spiegazioni elettronici	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1177 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Section 25 Power-Down State

Rev. 4.00 Sep 27, 2006 page 760 of 1130

REJ09B0327-0400

In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before

driving the

STBY pin low.

Do not change the state of the mode pins (MD1 and MD0) while the chip is in hardware standby

mode.

Hardware standby mode is cleared by means of the

STBY pin and the RES pin. When the STBY

pin is driven high while the

RES pin is low, the reset state is set and clock oscillation is started.

Ensure that the

RES pin is held low until the clock oscillation settles (at least 8 ms—the oscillation

settling time—when using a crystal oscillator). When the

RES pin is subsequently driven high, a

transition is made to the program execution state via the reset exception handling state.

25.7.2

Hardware Standby Mode Timing

Figure 25.4 shows an example of hardware standby mode timing.

When the

STBY pin is driven low after the RES pin has been driven low, a transition is made to

hardware standby mode. Hardware standby mode is cleared by driving the

STBY pin high, waiting

for the oscillation settling time, then changing the

RES pin from low to high.

Oscillator

RES

STBY

Oscillation

settling time

Reset exception

handling

Figure 25.4 Hardware Standby Mode Timing

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