HD6432142 datasheet(191/1177 Pages) RENESAS

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Section 5 Interrupt Controller

Rev. 4.00 Sep 27, 2006 page 147 of 1130

REJ09B0327-0400

The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while

the interrupt is masked.

5.6.2

Instructions That Disable Interrupts

Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these

instructions is executed, all interrupts except NMI are disabled and the next instruction is always

executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid

two states after execution of the instruction ends.

5.6.3

Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.

With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer

is not accepted until the move is completed.

With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt

exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this

case is the address of the next instruction.

Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the

following coding should be used.

L1:

EEPMOV.W

MOV.W

R4,R4

BNE

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