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HD6432142 Scheda tecnica(PDF) 218 Page - Renesas Technology Corp |
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HD6432142 Scheda tecnica(HTML) 218 Page - Renesas Technology Corp |
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218 / 1177 page ![]() Section 6 Bus Controller Rev. 4.00 Sep 27, 2006 page 174 of 1130 REJ09B0327-0400 T1 Address bus φ AS/IOS (IOSE = 0) Data bus T2 T3 T1 T2 T1 Full access T2 RD Burst access Only lower address changed Read data Read data Read data Figure 6.14 (a) Example of Burst ROM Access Timing (when AST = BRSTS1 = 1) T1 Address bus φ AS/IOS (IOSE = 0) Data bus T2 T1 T1 Full access RD Burst access Only lower address changed Read data Read data Read data Figure 6.14 (b) Example of Burst ROM Access Timing (when AST = BRSTS1 = 0) |
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