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HD6432142 Scheda tecnica(PDF) 246 Page - Renesas Technology Corp |
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HD6432142 Scheda tecnica(HTML) 246 Page - Renesas Technology Corp |
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246 / 1177 page ![]() Section 7 Data Transfer Controller (DTC) Rev. 4.00 Sep 27, 2006 page 202 of 1130 REJ09B0327-0400 Read Write Read Write Address φ DTC activation request DTC request Data transfer Data transfer Transfer information write Transfer information write Transfer information read Transfer information read Vector read Figure 7.12 DTC Operation Timing (Chain Transfer) 7.3.10 Number of DTC Execution States Table 7.8 lists execution phases for a single DTC data transfer, and table 7.9 shows the number of states required for each execution phase. Table 7.8 DTC Execution Phases Mode Vector Read I Register Information Read/Write J Data Read K Data Write L Internal Operation M Normal 1 6 113 Repeat 1 6 1 1 3 Block transfer 1 6 N N 3 Legend: N: Block size (initial setting of CRAH and CRAL) |
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