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7641 Scheda tecnica(PDF) 34 Page - Renesas Technology Corp |
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7641 Scheda tecnica(HTML) 34 Page - Renesas Technology Corp |
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34 / 385 page ![]() Rev.2.00 Aug 28, 2006 page 17 of 113 7641 Group REJ09B0336-0200 HARDWARE FUNCTIONAL DESCRIPTION Fig. 12 Port block diagram (1) (1) Ports P0, P1, P3 Data bus Direction register Port latch (3) Port P40 Data bus Direction register Port latch Expanded data memory access bit EDMA signal (5) Ports P43, P44 Data bus Direction register Port latch Timer count enabled Pulse output mode selected Timers X, Y output CNTR0, CNTR1 input (2) Port P2 Data bus Direction register Port latch P2 pull-up Key interrupt input (4) Ports P41, P42 Data bus Direction register Port latch Sub-clock (XCIN-XCOUT) stop bit INT0, INT1 interrupt input (6) Port P50 Data bus Direction register Port latch XCIN input |
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