7641 datasheet(9/385 Pages) RENESAS

9 / 385 page

Rev.2.00

Aug 28, 2006

page 5 of 13

7641 Group

REJ09B0336-0200

Fig. 45 Structure of USB frame number registers ..................................................................... 53

Fig. 46 Structure of USB endpoint 0 IN control register ........................................................... 54

Fig. 47 Structure of USB endpoint x (x = 1 to 4) IN control register ..................................... 55

Fig. 48 Structure of USB endpoint x (x = 1 to 4) OUT control register ................................. 56

Fig. 49 Structure of USB endpoint x IN max. packet size register ......................................... 57

Fig. 50 Structure of USB endpoint x OUT max. packet size register ..................................... 57

Fig. 51 Structure of USB endpoint x (x = 0 to 4) OUT write count registers ....................... 58

Fig. 52 Structure of USB endpoint x (x = 0 to 4) FIFO register ............................................. 58

Fig. 53 Structure of USB endpoint FIFO mode register ............................................................ 59

Fig. 54 Interrupt request circuit of data bus buffer .................................................................... 60

Fig. 55 Structure of master CPU bus interface related registers ............................................ 61

Fig. 56 Master CPU bus interface block diagram ...................................................................... 62

Fig. 57 Special count source generator block diagram ............................................................. 65

Fig. 58 Structure of special count source generator mode register ........................................ 66

Fig. 59 Frequency synthesizer block diagram ............................................................................ 67

Fig. 60 Structure of frequency synthesizer control register ...................................................... 68

Fig. 61 Reset circuit example ....................................................................................................... 69

Fig. 62 Reset sequence ................................................................................................................. 69

Fig. 63 Internal status at reset ..................................................................................................... 70

Fig. 64 Ceramic resonator or quartz-crystal oscillator external circuit .................................... 71

Fig. 65 External clock input circuit ............................................................................................... 71

Fig. 66 Structure of clock control register ................................................................................... 72

Fig. 67 Clock generating circuit block diagram .......................................................................... 73

Fig. 68 State transitions of clock .................................................................................................. 74

Fig. 69 Memory maps in processor modes other than single-chip mode ............................... 75

Fig. 70 Structure of CPU mode register A .................................................................................. 76

Fig. 71 Structure of CPU mode register B .................................................................................. 76

Fig. 72 Software wait timing diagram .......................................................................................... 77

Fig. 73 RDY wait timing diagram .................................................................................................. 77

Fig. 74 Extended RDY wait (software wait plus RDY input anytime wait) timing diagram .. 78

Fig. 75 Hold function timing diagram ........................................................................................... 79

Fig. 76 STA ($ zz), Y instruction sequence when EDMA enabled .......................................... 80

Fig. 77 LDA ($ zz), Y instruction sequence when EDMA enabled and T flag = “0” ............ 80

Fig. 78 LDA ($ zz), Y instruction sequence when EDMA enabled and T flag = “1” ............ 80

Fig. 79 Block diagram of built-in flash memory .......................................................................... 82

Fig. 80 Structure of flash memory control register .................................................................... 83

Fig. 81 CPU rewrite mode set/release flowchart ........................................................................ 84

Fig. 82 Program flowchart .............................................................................................................. 86

Fig. 83 Erase flowchart .................................................................................................................. 87

Fig. 84 Full status check flowchart and remedial procedure for errors .................................. 89

Fig. 85 Structure of ROM code protect control .......................................................................... 90

Fig. 86 ID code store addresses .................................................................................................. 91

Fig. 87 Pin connection diagram in standard serial I/O mode (1) ............................................ 95

Fig. 88 Pin connection diagram in standard serial I/O mode (2) ............................................ 96

Fig. 89 Timing for page read ........................................................................................................ 98

Fig. 90 Timing for reading status register ................................................................................... 98

Fig. 91 Timing for clear status register ....................................................................................... 99

Fig. 92 Timing for page program .................................................................................................. 99

Fig. 93 Timing for block erasing ................................................................................................. 100

Fig. 94 Timing for erase all blocks ............................................................................................ 100

Fig. 95 Timing for download ........................................................................................................ 101

Fig. 96 Timing for version information output ........................................................................... 102

List of figures

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