SH7052 datasheet(411/919 Pages) RENESAS

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Sample Setup Procedure for Channel 3 Input Capture Triggered by Channel 9 Compare-

Match: An example of the setup procedure for compare-match signal transmission is shown in

figure 10.62.

1. Set the port control register, corresponding to the port for signal input to the event counter, to

ATU event counter input.

2. Set the channel 3 timer I/O control register (TIOR3A, TIOR3B), and select the input capture

disable setting for the general registers (GR3A to GR3D). Input from pins TIO3A to TIO3D is

masked.

3. Select the event counter count edge with the EGSEL bits in the channel 9 timer control register

(TCR9A, TCR9B), and set the TRG3xEN bit to 1. Set the timing for capture in the general

4. Set bit STR3 to 1 in the timer start register (TSTR) to start the channel 3 free-running counter

(TCNT3).

5. Input a signal to the event counter input pin.

Note:

An interrupt request can be sent to the CPU upon channel 9 compare-match by making a

setting in the timer interrupt enable register (TIER), but an interrupt request cannot be sent

to the CPU upon channel 3 input capture.

Set port-ATU-II connection

Set input capture

Start counter

Start event input

Select compare-match

Input capture operation

Start

Figure 10.62 Sample Setup Procedure for Compare-Match Signal Transmission

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