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SH7052 Scheda tecnica(PDF) 415 Page - Renesas Technology Corp |
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SH7052 Scheda tecnica(HTML) 415 Page - Renesas Technology Corp |
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415 / 919 page ![]() 389 Contention between TCNT Write and Counter Clearing by Overflow: With channel 0 to 5 and 11 free-running counters (TCNT0, TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3 to TCNT5, TCNT11), if overflow occurs in the T2 state of a CPU write cycle, the write to TCNT has priority and TCNT is not cleared. Writing of 1 to the interrupt status flag (OVF) due to the overflow is performed in the same way as for normal overflow. The timing in this case is shown in figure 10.66. In this example, H'5555 is written at the point at which TCNT overflows. Pø T1 TCNT address 5555 (CPU write value) Internal write signal Overflow signal Interrupt status flag (OVF) TCNT input clock Address TCNT T2 FFFF 5556 Figure 10.66 Contention between TCNT Write and Overflow |
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