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SH7052 Scheda tecnica(PDF) 449 Page - Renesas Technology Corp

Il numero della parte SH7052
Spiegazioni elettronici  SuperHTM RISC engine
PDF  919 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 Scheda tecnica(HTML) 449 Page - Renesas Technology Corp

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12.3.4
Timing of Setting the Overflow Flag (OVF)
In interval timer mode, when TCNT overflows, the OVF flag of TCSR is set to 1 and an interval
timer interrupt (ITI) is simultaneously requested (figure 12.6).
H'FF
H'00
CK
TCNT
Overflow signal
(internal signal)
OVF
Figure 12.6 Timing of Setting OVF
12.3.5
Timing of Setting the Watchdog Timer Overflow Flag (WOVF)
When TCNT overflows in watchdog timer mode, the WOVF bit of RSTCSR is set to 1 and a
WDTOVF signal is output. When the RSTE bit in RSTCSR is set to 1, TCNT overflow enables an
internal reset signal to be generated for the entire chip (figure 12.7).
H'FF
H'00
CK
TCNT
Overflow signal
(internal signal)
WOVF
Figure 12.7 Timing of Setting WOVF



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