SH7052 datasheet(450/919 Pages) RENESAS

Il numero della parte	SH7052

Spiegazioni elettronici	SuperHTM RISC engine

PDF	919 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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12.4

Usage Notes

12.4.1

TCNT Write and Increment Contention

If a timer counter increment clock pulse is generated during the T3 state of a write cycle to TCNT,

the write takes priority and the timer counter is not incremented (figure 12.8).

Address

Internal

write signal

TCNT

input clock

TCNT

TCNT address

Counter write data

TCNT write cycle

Figure 12.8 Contention between TCNT Write and Increment

12.4.2

Changing CKS2 to CKS0 Bit Values

If the values of bits CKS2 to CKS0 in the timer control/status register (TCSR) are rewritten while

the WDT is running, the count may not increment correctly. Always stop the watchdog timer (by

clearing the TME bit to 0) before changing the values of bits CKS2 to CKS0.

12.4.3

Changing between Watchdog Timer/Interval Timer Modes

To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0)

before switching between interval timer mode and watchdog timer mode.

SH7052 Scheda tecnica(PDF) 450 Page - Renesas Technology Corp