SH7052 datasheet(515/919 Pages) RENESAS

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Figure 14.20 shows an example of SCI transmit operation.

Bit 0

Bit 1

Bit 7

Bit 0

Bit 1

Bit 6

Serial clock

Serial data

Transfer direction

Bit 7

TXI interrupt

handler writes

data in TDR and

clears TDRE to 0

1 frame

TXI interrupt

request

TDRE

TEND

LSB

MSB

TEI interrupt

request

TXI interrupt

request

Figure 14.20 Example of SCI Transmit Operation

SCI serial transmission operates as follows.

1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that

the transmit data register (TDR) contains new data and loads this data from TDR into the

transmit shift register (TSR).

2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts

transmitting. If the transmit-data-empty interrupt enable bit (TIE) in SCR is set to 1, the SCI

requests a transmit-data-empty interrupt (TXI) at this time.

If clock output mode is selected, the SCI outputs eight serial clock pulses. If an external clock

source is selected, the SCI outputs data in synchronization with the input clock. Data is output

from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7).

3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads

data from TDR into TSR, then begins serial transmission of the next frame. If TDRE is 1, the

SCI sets the TEND bit in SSR to 1, transmits the MSB, then holds the transmit data pin (TxD)

in the MSB state. If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a transmit-

end interrupt (TEI) is requested at this time.

4. After the end of serial transmission, the SCK pin is held in the high state.

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