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SH7052 Scheda tecnica(PDF) 182 Page - Renesas Technology Corp |
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SH7052 Scheda tecnica(HTML) 182 Page - Renesas Technology Corp |
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182 / 919 page ![]() 156 Table 9.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits (cont) RS4 RS3 RS2 RS1 RS0 DMAC Transfer Request Source DMAC Transfer Request Signal Transfer Source Transfer Destination Bus Mode 10001 ATU-II ICI0A (ICR0A input capture generation) Don’t care* Don’t care* Burst/cycle- steal 1 0 ATU-II ICI0B (ICR0B input capture generation) Don’t care* Don’t care* Burst/cycle- steal 1 ATU-II ICI0C (ICR0C input capture generation) Don’t care* Don’t care* Burst/cycle- steal 1 0 0 ATU-II ICI0D (ICR0D input capture generation) Don’t care* Don’t care* Burst/cycle- steal 1 ATU-II CMI6A (CYLR6A compare-match generation) Don’t care* Don’t care* Burst/cycle- steal 1 0 ATU-II CMI6B (CYLR6B compare-match generation) Don’t care* Don’t care* Burst/cycle- steal 1 ATU-II CMI6C (CYLR6C compare-match generation) Don’t care* Don’t care* Burst/cycle- steal 1000 ATU-II CMI6D (CYLR6D compare-match generation) Don’t care* Don’t care* Burst/cycle- steal 1 ATU-II CMI7A (CYLR7A compare-match generation) Don’t care* Don’t care* Burst/cycle- steal 1 0 ATU-II CMI7B (CYLR7B compare-match generation) Don’t care* Don’t care* Burst/cycle- steal 1 ATU-II CMI7C (CYLR7C compare-match generation) Don’t care* Don’t care* Burst/cycle- steal 1 0 0 ATU-II CMI7D (CYLR7D compare-match generation) Don’t care* Don’t care* Burst/cycle- steal Legend: SCI0, SCI1, SCI2, SCI3, SCI4: Serial communication interface channels 0 to 4 A/D0, A/D1: A/D converter channels 0, 1 HCAN: Hitachi controller area network channel 0 ATU-II: Advanced timer unit TDR0, TDR1, TDR2, TDR3, TDR4: SCI0 to SCI4 transmit data registers RDR0, RDR1, RDR2, RDR3, RDR4: SCI0 to SCI4 receive data registers ADDR0 to ADDR11: A/D0 data registers |
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