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SH7708 Scheda tecnica(PDF) 346 Page - Renesas Technology Corp |
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SH7708 Scheda tecnica(HTML) 346 Page - Renesas Technology Corp |
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346 / 633 page ![]() 328 12.2.11 Hour Alarm Register (RHRAR) The hour alarm register (RHRAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded hour section counter RHRCNT of the RTC. When the ENB bit is set to 1, a comparison with the RHRCNT value is performed. From among the RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range that can be set is 00–23 (decimal) + ENB bit. Errant operation will result if any other value is set. The ENB bit in RHRAR is initialized by a power-on reset. The remaining RHRAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Contents are retained in a manual reset and in standby mode. Bit: 7 6 5 4 3 2 1 0 Bit name: ENB — 10 hours 1 hour Initial value: 0 0 — — — — — — R/W: R/W R R/W R/W R/W R/W R/W R/W 12.2.12 Day of the Week Alarm Register (RWKAR) The day of the week alarm register (RWKAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded day of week section counter RWKCNT of the RTC. When the ENB bit is set to 1, a comparison with the RWKCNT value is performed. From among the RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range that can be set is 0–6 (decimal) + ENB bit. Errant operation will result if any other value is set. The ENB bit in RWKAR is initialized by a power-on reset. The remaining RWKAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Contents are retained in a manual reset and in standby mode. Bit: 7 6 5 4 3 2 1 0 Bit name: ENB — — — — Day of week Initial value: 0 0 0 0 0 — — — R/W: R/W R R R R R/W R/W R/W |
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