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SH7708 Scheda tecnica(PDF) 78 Page - Renesas Technology Corp |
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SH7708 Scheda tecnica(HTML) 78 Page - Renesas Technology Corp |
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78 / 633 page ![]() 60 3.3 TLB Functions 3.3.1 Configuration of the TLB The TLB caches address translation table information located in external memory. The address translation table stores the physical page number translated from the virtual page number and the control information for the page, which is the unit of address translation. Figure 3.4 shows the overall TLB configuration. The TLB is 4-way set associative with 128 entries. There are 32 entries for each way. Figure 3.5 shows the configuration of virtual addresses and TLB entries. Entry 1 Address array Data array Entry 0 Entry 1 Entry 31 Way 0–3 Way 0–3 VPN(11–10) VPN(31–17) ASID(7–0) V Entry 0 Entry 31 PPN(31–10) PR(1–0) SZ C D SH Figure 3.4 Overall Configuration of the TLB |
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