SH7708 datasheet(98/633 Pages) RENESAS

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3.6.3

Usage Examples

Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry’s

V bit. When the A bit is 1, the VPN and ASID specified by the write data is compared to the VPN

and ASID within the TLB entry selected by the entry address and data is written to the matching

way. If no match is found, there is no operation. R0 specifies the write data and R1 specifies the

address.

; R0=H'1547 381C

R1=H'F201 3080

; MMUCR.IX=0

; VPN(31–17)=B'0001 0101 0100 011

VPN(11–10)=B'10

ASID=B'0001 1100

; corresponding entry association is made from the entry selected by

; the VPN(16–12)=B'1 0011 index, the V bit of the hit way is cleared to

; 0,achieving invalidation.

MOV.L

R0,@R1

Reading the Data of a Specific Entry: This example reads the data section of a specific TLB

entry. The bit order indicated in the data field in figure 3.14 (2) is read. R0 specifies the address

and the data section of a selected entry is read to R1.

; R0=H'F300 4300

VPN(16-12)=B'00100

Way 3

; MOV.L @R0,R1

3.7

Usage Note

Instructions that manipulate the MD or BL bit in register SR (the LDC Rm, SR instruction, LDC

@Rm+, SR instruction, and RTE instruction) and the following instruction, or the LDTLB

instruction, should be used with the TLB disabled or in a fixed physical address space (the P1 or

P2 space).

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