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PSD4235G2 Scheda tecnica(PDF) 79 Page - STMicroelectronics

Il numero della parte PSD4235G2
Spiegazioni elettronici  Flash In-System-Programmable Peripherals for 16-Bit MCUs
PDF  93 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD4235G2 Scheda tecnica(HTML) 79 Page - STMicroelectronics

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PSD4000 Series
Preliminary Information
76
-90
-12
Slew
TURBO
Rate
Symbol
Parameter
Conditions
Min
Max
Min
Max
OFF
(Note 1)
Unit
tPD
PLD Input Pin/Feedback to
38
43
Add 20
Sub 6
ns
PLD Combinatorial Output
tARD
PLD Array Delay
23
27
ns
PLD Combinatorial Timing (3.0 V to 3.6 V Versions)
NOTE: 1. Fast Slew Rate output available on Port C and F.
-90
-12
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
tLVLX
ALE or AS Pulse Width
22
24
tAVLX
Address Setup Time
(Note 1)
7
9
ns
tLXAX
Address Hold Time
(Note 1)
8
10
ns
tAVWL
Address Valid to Leading
Edge of WR
(Notes 1 and 3)
15
18
ns
t SLWL
CS Valid to Leading Edge of WR
(Note 3)
15
18
ns
t DVWH
WR Data Setup Time
(Note 3)
40
45
ns
t WHDX
WR Data Hold Time
(Note 3)
5
8
ns
t WLWH
WR Pulse Width
(Note 3)
40
45
ns
tWHAX1
Trailing Edge of WR to Address Invalid
(Note 3)
8
10
ns
tWHAX2
Trailing Edge of WR to DPLD Address
(Notes 3 and 4)
0
0
ns
Input Invalid
tWHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
33
33
ns
tAVPV
Address Input Valid to Address
(Note 2)
30
35
ns
Output Delay
Write Timing (3.0 V to 3.6 V Versions)
NOTES: 1. Any input used to select an internal PSD4000 function.
2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E, DS, LDS, UDS, WRL, and WRH signals.
4. tWHAX2 is Address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory.
Microcontroller Interface – PSD4000 AC/DC Parameters
(3.0 V to 3.6 V Versions)



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