MPC5634M datasheet(60/106 Pages) FREESCALE

60 / 106 page

MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

3.7

Signal details

Table 5 contains details on the multiplexed signals that appear in Table 3, “MPC563xM signal properties”.

Table 5. Signal details

Signal

Module or Function

Description

CLKOUT

Clock Generation

MPC5634M clock output for the external/calibration bus interface

EXTAL

Clock Generation

Input pin for an external crystal oscillator or an external clock

source based on the value driven on the PLLREF pin at reset.

EXTCLK

Clock Generation

External clock input

PLLREF

Clock Generation

PLLREF is used to select whether the oscillator operates in xtal

mode or external reference mode from reset. PLLREF=0 selects

external reference mode.

XTAL

Clock Generation

Crystal oscillator input

SCK_B_LVDS–

SCK_B_LVDS+

DSPI

LVDS pair used for DSPI_B TSB mode transmission

SOUT_B_LVDS–

SOUT_B_LVDS+

DSPI

LVDS pair used for DSPI_B TSB mode transmission

SCK_C_LVDS–

SCK_C_LVDS+

DSPI

LVDS pair used for DSPI_C TSB mode transmission

SOUT_C_LVDS–

SOUT_C_LVDS+

DSPI

LVDS pair used for DSPI_C TSB mode transmission

PCS_B[0]

PCS_C[0]

DSPI_B – DSPI_C

Peripheral chip select when device is in master mode—slave

select when used in slave mode

PCS_B[1:5]

PCS_C[1:5]

DSPI_B – DSPI_C

Peripheral chip select when device is in master mode—not used

in slave mode

SCK_B

SCK_C

DSPI_B – DSPI_C

DSPI clock—output when device is in master mode; input when

in slave mode

SIN_B

SIN_C

DSPI_B – DSPI_C

DSPI data in

SOUT_B

SOUT_C

DSPI_B – DSPI_C

DSPI data out

CAL_ADDR[12:30]

Calibration Bus

The CAL_ADDR[12:30] signals specify the physical address of

the bus transaction.

CAL_CS[0:3]

Calibration Bus

CSx is asserted by the master to indicate that this transaction is

targeted for a particular memory bank on the Primary external

bus.

CAL_DATA[0:15]

Calibration Bus

The CAL_DATA[0:15] signals contain the data to be transferred

for the current transaction.

CAL_OE

Calibration Bus

OE is used to indicate when an external memory is permitted to

drive back read data. External memories must have their data

output buffers off when OE is negated. OE is only asserted for

chip-select accesses.

CAL_RD_WR

Calibration Bus

RD_WR indicates whether the current transaction is a read

access or a write access.

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