CS42324 datasheet(32/71 Pages) CIRRUS

32 / 71 page

DS721A6

CS42324

4.2.5

Digital Interface Formats

Each converter (ADC, DAC1, and DAC2) has independent selection for serial formats (I²S, Left-Justified,

etc.). Data is clocked out of the ADC or into the DAC on the rising edge of SCLK. Figures 13-17 illustrate

the general structure of each format. Refer to “Switching Characteristics - Serial Audio” on page 22 or

“Switching Characteristics - Serial Audio (Cont.)” on page 23 for exact timing relationship between clocks

and data. For a complete overview of Serial Audio Interface Formats, please reference Application Note

AN282.

4.2.6

Synchronization of Multiple Devices

In systems where multiple ADCs and DACs are required, care must be taken to achieve simultaneous

sampling. To ensure synchronous sampling, the master clocks and left/right clocks must be the same for

all of the CS42324’s in the system. If only one master clock source is needed, one solution is to place one

CS42324 in Master Mode, and slave all of the other devices to the one master.

DIF (Pin 5) Setting

Selection

Left-Justified Interface

I²S Interface

Table 8. Hardware Mode Interface Format Control

LRCKx

SCLKx

MS B

LS B

MS B

LS B

AOUTxA

L eft C han n el

Rig ht C h an nel

SDOUT

SDIN1/2

AOUTxB

MSB

AINxA

AINxB

Figure 13. Left-Justified up to 24-Bit Data

LRCKx

SCLKx

MS B

LS B

MS B

LS B

AOUTxA

L eft C han n el

Rig ht C h an nel

SDOUT

SDIN1/2

AOUTxB

MSB

AINxA

AINxB

Figure 14. I²S up to 24-Bit Data

LRCKx

SCLKx

MS B

LS B

MS B

LS B

AOUTxA

Le ft C h a nne l

R i g h t C h a n n e l

SDOUT

SDIN1/2

AOUTxB

AINxA

AINxB

Figure 15. Right-Justified 16-Bit Data, Right-Justified 24-Bit Data

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