FMP3217BAx

CMOS LPRAM

Revision 0.3

Feb. 2007

10

LOW POWER MODES

1. Mode Register Set

A0

A1

A2

A3

A4

A20 ~ A5

Array Refresh Area

Half Selection

Array On/Off

on /ZZ

ZZ

Enable/Disable

0

/ZZ Enable/Disable

DPD Disable (Default)

1

Deep Power Down Enable

0

Type

A4

Array On/Off on /ZZ

Reduced Memory Size Mode

1

Partial Array Refresh Mode (Default)

0

Type

A3

Note: If the register is written to enable the Deep

Power Down, the part will go into Deep Power Down

during the following time that /ZZ is driven low and

there is no MRS update. When /ZZ is driven high, all

of the register settings will return to default state for

the part (i.e. full array refresh, Deep Power Down

Disabled).

Note: The RMS(Reduced Memory Size) mode is enabled after

/ZZ goes high and remains enabled after /ZZ goes high. To

change to a different mode, the mode register will have to be

rewritten.

Half Selection (Top / Bottom)

Top

1

Bottom (Default)

0

Type

A2

Array Refresh Area

RFU

1

0

½Array

0

1

1

0

A1

¼Array

1

Full Array (Default)

0

Type

A0

2. MRS Update

Address

/CS

/UB, /LB

/WE

tWC

tWR(4)

tBW

tWP(1)

tCW(2)

tAS(3)

tAW

/ZZ

tZZWE

Register Write Start

Register Write

Complete

Register Update

Complete

The register update take place on the rising edge of /ZZ. Once the register is updated, the next time /ZZ goes low, without any

updates to the register starting within the tZZWE max time of 1us, the part will refresh the array selected. The data bus is a

don’t care When /ZZ is low during the register updates.